Reliability of VLSI Linear Arrays with Redundant Links

Reliability is one of the most important attributes of any system. Adding redundancy is one way to improve the reliability. In this paper, we consider linear VLSI arrays in which each processor has a set of redundant links to bypass faulty processor(s). It is known that patterns of faults occurring at strategic locations in such arrays can be catastrophic and may render the system unusable regardless of its component redundancy and of its reconfiguration capabilities. Assuming a number of faulty processors (i.e., a fault pattern which may or may not be catastrophic) and a set of redundant links (i.e., link configuration), we use combinatorial modelling to evaluate the reliability of the linear VLSI arrays. Moreover, we also discuss how the choice of a link configuration can play a role in reliability improvement.